I need an engineer who can take my functional requirements and turn them into clean, synthesizable SystemVerilog that runs on the DE-10 FPGA kit. The work covers the full RTL flow—coding the logic, building self-checking test-benches, running ModelSim simulations, and closing on timing before hand-off.

You are free to follow your own coding style so long as the code is readable, well-commented, and synthesizes without warnings. The critical point is that every module is fully verified: all corner cases exercised, assertions in place, coverage collected, and a concise report delivered alongside waveform evidence.

I’m based in Ho Chi Minh City and would strongly prefer someone who can meet on-site when needed to review schematics, probe the board, and iterate quickly once the bitstream is loaded. Remote collaboration is possible, but local availability will weigh heavily in my decision.

Final deliverables
• SystemVerilog RTL source targeting the DE-10
• Self-checking ModelSim test-benches with assertion coverage
• Simulation logs, waveforms, and coverage reports demonstrating pass criteria
• Synthesis/timing report confirming the design meets the board’s constraints
• Brief hand-over document so I can maintain and extend the design later

If you have a solid track record of taping out—or better yet, shipping—FPGA designs of similar complexity, I’d like to hear how you’d approach this project and your estimated timeline.